Modern integrated circuits generally contain several layers of interconnect structures fabricated above a substrate. The substrate may have active devices and/or conductors that are connected by the interconnect structure.
Interconnect structures, typically comprising trenches and vias, are usually fabricated in, or on, an interlayer dielectric (LD). It is generally accepted that, the dielectric material in each ILD should have a low dielectric constant (k) to obtain low capacitance between conductors. Decreasing this capacitance between conductors, by using a low dielectric constant (k), results in several advantages. For instance, it provides reduced RC delay, reduced power dissipation, and reduced cross-talk between the metal lines.
Some materials that may be used for ILDs are sol gel dielectrics. Sol gel materials, such as silica sol gels, start as a sols, or solutions, and go through a phase transition to form a wet gel. Typically, the solvent is extracted from the wet gel to form an ILD, with pores distributed through out the ILD. These pores allow sol gel materials to obtain low k dielectrics. However, these dielectrics often posses bad mechanical properties, which leads to fragility during hardening and semiconductor fabrication. For example, ILDs with weak mechanical properties may crack or otherwise break down during harsh fabrications steps, such as chemical mechanical polish (CMP).
Another material that may be used for ILDs is zeolite or silica zeolite. Zeolite films are advantageous in that they have a relatively uniform pore distribution and have good mechanical strength. Furthermore, zeolite films have dielectric constants (k values) in the range of 2 and below. Yet, zeolite is a crystalline structure, which makes forming a uniform film extremely difficult. Discontinuities in an ILD may cause line to line leakage or diffusion into the ILD materials.